1. Technical Field
The present inventive concept relates to nonvolatile memory devices, and more particularly, to a charge trap flash memory device using an insulation layer as a charge storage layer and an erasing method thereof.
2. Discussion of the Related Art
Flash memory is a non-volatile memory device that can be electrically erased and programmed A flash memory cell is made of a floating gate transistor that includes a floating gate electrically isolated between a control gate and a channel. A flash memory cell may store bit information by injecting an electric charge into a conductive floating gate insulated with an insulation layer. However, unwanted charges may migrate to the floating gate, due to capacitive coupling between memory cells or between a memory cell and a selection transistor, thus causing the stored electric charge to change. Further, the capacitive coupling may worsen as flash memories increase their degree of integration. To alleviate the effects of capacitive coupling between conductive floating gates, a charge storage layer of Si3N4, Al2O3, HfAlO, or HfSiO (e.g., a layer having a charge trap site) may be used in place of a conductive floating gate. A flash memory employing such a charge storage layer in its cells is called a charge trap flash (CTF) memory.
The CTF memory has a transient characteristic in which after a program or erase voltage is applied for a program or erase operation, electrons/holes in a charge storage layer become stabilized in terms of energy such that the injection/emission of the electrons/holes to/from the charge storage layer does not occur. According to the transient characteristic, a CTF memory cell may have a threshold voltage Vth that becomes stable after a predetermined time elapses from the time when a program or erase voltage is applied to the CTF memory.
The transient characteristic of the CTF memory may be changed according to external influences such as temperature, humidity, pressure, and electromagnetic force. For example, the transient characteristic of the CTF memory is dependent on a change in temperature. Therefore, a time for stabilizing electrons/holes in a charge storage layer is closely related to a time consumed by program and erase operations and consequently whether an error occurs or not.
For example, when the CTF memory operates at a cold temperature below that of its verified operating range, a time for stabilizing electrons/holes in a charge storage layer may change. Accordingly, an erase verify operation may be performed prior to stabilization is secured and therefore, an error occurrence frequency of an erase operation may be increased. This may cause malfunctions of the CTF memory and may deteriorate data reliability. Further, the increase of errors in an erase operation increases the number of repetitions of an erase loop, such that a high voltage stress (e.g., an erase voltage of 20V) applied to the CTF memory is increased. Further, the increased high voltage stress applied to the CTF memory also shortens the life span thereof.
Accordingly, there is a need for the CTF memory to properly operate in temperature extremes outside its verified operating rage.